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HV100/HV101 3-Pin Hotswap, Inrush Current Limiter Controllers (Negative Supply Rail)
Features
33% Smaller than SOT-232 Pass Element is Only External Part No Sense Resistor required Auto-adapt* to Pass Element Short Circuit Protection* UV & POR Supervisory Circuits 2.5s Auto Retry 10V to 72V Input Voltage Range 0.6mA Typical Operating Supply Current Built in Clamp for AC Path Turn On Glitch
General Description
The HV100 and the HV101 are 3-pin hotswap controllers available in the SOT-223 package, which require no external components other than a pass element. The HV100 and the HV101 contain many of the features found in hotswap controllers with 8 pins or more, and which generally require many external components. These features include undervoltage (UV) detection circuits, power on reset (POR) supervisory circuits, inrush current limiting, short circuit protection, and auto-retry. In addition, the HV100 and the HV101 use a patent pending mechanism to sample and adapt to any pass element, resulting in consistent hotswap profiles without any programming. The only difference between the HV100 and the HV101 is the internally set undervoltage (UV) threshold.
*Patents Pending
Applications
-48V Central Office Switching (line cards) +48V Server Networks +48V Storage Area Networks +48V Peripherals, Routers, Switches +24V Cellular and Fixed Wireless (bay stations, line cards) +24V Industrial Systems +24V UPS Systems -48V PBX & ADSL Systems (line cards) Distributed Power Systems Powered Ethernet for VoIP
Typical Application Circuit and Waveforms
GND
VPP
400F GATE DC/DC Converter
+5V COM
HV100
VNN
-48V
IRF530
HV100/HV101
Ordering Information
UV Options 34V 14V Package Options 3-Pin SOT-223 HV100K5 HV101K5 HV100K5-G HV101K5-G
Pin Configuration
-G indicates package is RoHS compliant (`Green')
1 VPP
2 VNN (Top View)
3 GATE
3-Lead SOT-223
Absolute Maximum Ratings
Parameter VPP Input Voltage Operating Ambient Temperature Range Operating Junction Temperature Range Storage Temperature Range Value -0.3V - 75.0V -40oC to +85oC -40oC to +125oC -65oC to +150oC GATE
Pin Description
Pin VPP VNN Function Positive voltage power supply to the circuit. Negative voltage power supply to the circuit. Gate driver output for the external n-Channel MOSFET
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground.
DC Electrical Characteristics (V
Sym. Parameter Supply (Referenced to VPP pin) VNN INN Supply Voltage Supply Current
H
= VDD = 12V, VL = VSS = GND = 0V, VOE = 3.3V, TJ = 25C)
Min.
Typ.
Max.
Units
Conditions
-72 -
0.6
UV 1.0
V mA
--VNN = -48.0V
UV Control (Referenced to VNN pin) VUVL VUVH UV Threashold (High to Low) 30 12.3 34 14 3 1 38 15.7 V V V V HV100 HV101 HV100 HV101
UV Hysteresis
Gate Drive Output (Referenced to VNN pin) VGATE SRGATE IGATEDOWN IPULLUP Maximum Gate Drive Voltage Initial Slew Rate Gate Drive Pull-Down Current (Sinking) Post Hot Swap Pull-Up Current 10 1.5 8 6 12 16 11 14 3.75 V V/ms mA A --CGATE = 1nF VGATE = 1.0V; VPP = 11.5V VGATE = 6.0V
2
HV100/HV101
DC Electrical Characteristics (cont.)
Sym Parameter Min Typ Max Units Conditions Timing Control (Referenced to VNN pin) tPOR tARD Insertion POR Delay Auto Restart Delay 1.5 1.25 3.5 2.5 5.5 3.75 ms s -----
Example Electrical Results (Using IRF530) ILIM ILIM ILIM ISHORT tSHORT GATE tHS Max Inrush Current During Hotswap Max Inrush Current During Hotswap Max Inrush Current During Hotswap Max Current Into a Short Shorted Load Detect Time Initial Rate of Rise of Gate Hot Swap Period to Full Gate Value 1.4 2.5 3.1 4.0 1.0 2.5 12.5 A A A A ms V/ms ms IRF530 external MOSFET, CLOAD = 100F IRF530 external MOSFET, CLOAD = 200F IRF530 external MOSFET, CLOAD = 300F IRF530 external MOSFET, RLOAD = <<1.5 IRF530 external MOSFET, RLOAD = <<1.5 IRF530 external MOSFET, any CLOAD IRF530 external MOSFET, any CLOAD
Functional Block Diagram
VPP
Regulator
UVLO
Reference Generator
UV
POR Timer Logic Restart Timer
GATE
VNN
3
HV100/HV101
Functional Description
Insertion into Hot Backplanes
Telecom, data network and some computer applications require the ability to insert and remove circuit cards from systems without powering down the entire system. Since all circuit cards have some filter capacitance on the power rails, which is especially true in circuit cards or network terminal equipment utilizing distributed power systems, the insertion can result in high inrush currents that can cause damage to connector and circuit cards and may result in unacceptable disturbances on the system backplane power rails. The HV100 and HV101 are designed to facilitate the insertion and removal of these circuit cards or connection of terminal equipment by eliminating these inrush currents and powering up these circuits in a controlled manner after full connector insertion has been achieved. The HV100 and HV101 are intended to provide this control function on the negative supply rail. After completion of a full POR period, the MOSFET gate autoadapt operation begins. A reference current source is turned on which begins to charge an internal capacitor generating a ramp voltage which rises at a slew rate of 2.5 V/ms. This reference slew rate is used by a closed loop system to generate a GATE output current to drive the gate of the external N-channel MOSFET with a slew rate that matches the reference slew rate. Before the gate crosses a reference voltage, which is well below the VTH of industry standard MOSFETs, the pull-up current value is stored and the auto-adapt loop is opened. This stored pull-up current value is used to drive the gate during the remainder of the hot swap period. The result is a normalization with CISS , which for most MOSFETs scales with CRSS. The MOSFET gate is charged with a current source until it reaches its turn on threshold and starts to charge the load capacitor. At this point the onset of the Miller Effect causes the effective capacitance looking into the gate to rise, and the current source charging the gate will have little effect on the gate voltage. The gate voltage remains essentially constant until the output capacitor is fully charged. At this point the voltage on the gate of the MOSFET continues to rise to a voltage level that guarantees full turn on of the MOSFET. It will remain in the full on state until an input under voltage condition is detected. If the circuit attempts turn on into a shorted load, then the Miller Effect will not occur. The gate voltage will continue to rise essentially at the same rate as the reference ramp indicating that a short circuit exists. This is detected by the control circuit and results in turning off the MOSFET initiating a 2.5 second delay, after which a normal restart is attempted. If at any time during the start up cycle or thereafter, the input voltage falls below the UV threshold the GATE output will be pulled down to VNN, turning off the N-channel MOSFET and all internal circuitry is reset. A normal restart sequence will be initiated once the input voltage rises above the UVLO threshold plus hysteresis.
Description of Operation
On initial power application the high input voltage internal regulator seeks to provide a regulated supply for the internal circuitry. Until the proper internal voltage is achieved all circuits are held reset by the internal UVLO and the gate to source voltage of the external N-channel MOSFET is held off. Once the internal regulator voltage exceeds the UVLO threshold, the input undervoltage detection circuit (UV) senses the input voltage to confirm that it is above the internally programmed threshold. If at any time the input voltage falls below the UV threshold, all internal circuitry is reset and the GATE output is pulled down to VNN. UVLO detection works in conjunction with a power on reset (POR) timer of approximately 3.5ms to overcome contact bounce. Once the UVLO is satisfied, the gate is held to VNN until a POR timer expires. Should the UV monitor toggle before the POR timer expires, the POR timer will be reset. This process will be repeated each time UVLO is satisfied until a full POR period has been achieved.
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HV100/HV101
Application Information
Turn On Clamp
Hotswap controllers using a MOSFET as the pass element all include a capacitor divider from VPP to VNN through CLOAD, CRSS and CGS. In most competitive solutions a large external capacitor is added to the gate of the pass element to limit the voltage on the gate resulting from this divider. In those instances, if a gate capacitor is not used the internal circuitry is not available to hold off the gate, and therefore a fast rising voltage input will cause the pass element to turn on for a moment. This allows current spikes to pass through the MOSFET. The HV100 and HV101 include a built-in clamp to ensure that this spurious current glitch does not occur. The built-in clamp will work for the time constants of most mechanical connectors. There may be applications, however, that have rise times that are much less than 1s (100's of ns). In these instances it may be necessary to add a capacitor from the MOSFET gate to source to clamp the gate and suppress this current spike. In these cases the current spike generally contains very little energy and does not cause damage even if a capacitor is not used at the gate.
Short Circuit Protection
The HV100 and HV101 provide short circuit protection by shutting down if the Miller Effect associated with hotswap does not occur. Specifically, if the output is shorted then the gate will rise without exhibiting a "flat response". Due to the fact that we have normalized the hotswap period for any pass element, a timer can be used to detect if the gate voltage rises above a threshold within that time, indicating that a short exists. The diagram below shows a typical turn on sequence with the load shorted, resulting in a peak current of 4A.
Auto-adapt Operation
The HV100 and HV101 auto-adapt mechanism provides an important function. It normalizes the hotswap period regardless of pass element or load capacitor for consistent hotswap results. By doing this it allows the novel short circuit mechanism to work because the mechanism requires a known time base. The maximum current that may occur during this period can be controlled by adding a resistor in series with the source of the MOSFET. The lower graph shows the same circuit with a 100m resistor inserted between source and VNN. In this case the maximum current is 25% smaller.
The above diagram illustrates the effectiveness of the autoadapt mechanism. In this example three MOSFETs with different CISS and RDSON values are used. The top waveform is the hotswap current, while the bottom waveform is the gate voltage. As can be seen, the hotswap period is normalized, the initial slope of the gate voltage is approximately 2.5V/ms regardless of the MOSFET, and the total hotswap period and peak currents are a function of a MOSFET type dependent constant multiplied by CLOAD. Typically if MOSFETs of the same type are used, the hotswap results will be extremely consistent. If different types are used they will usually exhibit minimal variation.
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For most applications and pass elements, the HV100 and HV101 provides adequate limiting of the maximum current to prevent damage without the need for any external components. The 2.5s delay of the auto-retry circuit provides time for the pass element to cool between attempts.
HV100/HV101
Auto-Retry
Not only do the HV100 and HV101 provide short circuit protection in a 3-pin package, they also includes a 2.5s built in auto-restart timer. The HV100 and HV101 will continuously try to turn on the system every 2.5s, providing sufficient time for the pass element to cool down after each attempt. All of the above are possible with a minimum number of external components. i) To adjust inrush current with an external component simply connect a capacitor (CFB) from drain to gate of the MOSFET. The inrush calculation then becomes: IINRUSH(PEAK) = (CFB + CISS)/(CRSS + CFB) * 2.5e3 * CLOAD Note that a resistor (approximately 10K) needs to be added in series with CFB to create a zero in the feedback loop and limit the spurious turn on which is now enhanced by the larger divider element. To increase undervoltage lockout simply connect a Zener diode in series with the VPP pin.
ii)
iii) If the VPP rises particularly fast (>48e6V/s) then it may be desirable to connect a capacitor from gate to source of the MOSFET to provide a path for the power application transient spike, which is now too fast for the internal clamping mechanism.
Calculating Inrush Current
As can be seen in the diagram below, for a standard pass element, the HV100 and HV101 will normalize the hotswap time period against load capacitance. For this reason the current limit will increase with increasing value of the load capacitance. Inrush can be calculated from the following formula: IINRUSH(PEAK) = (CISS / CRSS) * 2.5e3 * CLOAD This is a surprisingly consistent result because for most MOSFETs of a particular type the ratio of CISS / CRSS is relatively constant (though notice from the plot that there is some variation) even while the absolute value of these and other quantities vary. Based on this, the inrush current will vary primarily with CLOAD. This makes designing with the HV100 and HV101 particularly easy because once the pass element is chosen, the period is fixed and the inrush varies with CLOAD only.
iv) To limit the peak current during a short circuit, a resistor in series with the source of the MOSFET may help.
Implementing PWRGD Control
Due to the HV100 and HV101's small footprint, it is possible to create an open drain PWRGD signal using external components and still maintain a size comparable with the smallest hotswap controllers available elsewhere. To accomplish this an external MOSFET may be used in conjunction with the gate output. Simply use a high impedance divider (10M) sized so that the open drain PWRGD MOSFET threshold will only be reached once the HV100/HV101's gate voltage rises well above the current limit value required by the external MOSFET pass device. Alternatively a Zener diode between the gate output and the PWRGD MOSFET gate set at a voltage higher than the maximum pass element Vt will also work.
Programming the HV100 and HV101
The HV100 and HV101 require no external components other than a pass element to provide the functionality described thus far. In some applications it may be useful to use external components to adjust the maximum allowable inrush current, adjust UVLO, or to provide additional gate clamping if the supply rails have rise times below 1ms.
HV100
PWGRD
6
HV100/HV101
Powered Ethernet (Power-Over-LAN) / VoIP Solutions
Powered Device (PD)
DC / DC Converter
VPP
HV101
PHY
VNN
+ 3.3V/5V
GATE
HV101 Used as a UVLO & Load Switch
7
HV100/HV101
3-Lead SOT-223 Package (K5)
0.12 0.004 (3.05 0.10) 0.256 0.008 (6.50 0.20)
0.2755 0.0115 (7.00 0.30) 0.138 0.008 (3.50 0.20)
Measurement Legend =
Dimensions in Inches (Dimensions in Millimeters)
1
0.0905 TYP. (2.30)
0.037 0.004 (0.95 0.10)
13 3e 0.012 0.002 (0.30 0.05)
0.0635 0.0035 (1.60 0.10)
0.0024 0.0016 (0.06 0.04)
0.0295 0.0035 (0.75 0.10) 0.181 TYP (4.60)
0.067 0.004 (1.20 0.10)
10e Max
13 3e
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV100_HV101 A122806
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